Semiconductor integrated circuit

ABSTRACT

The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.

TECHNICAL FIELD

The present invention relates to a semiconductor integrated circuit,particularly to a semiconductor integrated circuit applicable to LSI fora general use processor, a signal processing processor, an imageprocessing processor or the like partially including logical operationcircuits.

BACKGROUND OF THE INVENTION

Conventionally, in realizing a large scale logical operation circuit,there has widely been used systems of gate array, standard cell (or cellbase integrated circuit) and the like. In these integrated circuits, apartial circuit referred to as cell is prepared previously. A cellsignifies a small scale logical operation circuit in which layout of amask pattern has been completed, normally, a plurality of them arearranged on the same chip. In respect of a cell, normally, other thanmask layout, positions and areas of input and output terminals, anoperational speed, power consumption and the like are prepared. A celllibrary stores information with regard to the cell in a storage devicefor assisting design of an integrated circuit. There has been known adesign system using such cells, which is combined with a circuitreferred to as a pass transistor circuit.

Pass transistor circuits have been introduced as “DifferentialPass-transistor Logic” in IEEE Journal of Solid-State Circuits, Vol.sc-22, No. 2, April 1987 pp216-pp222 (hereinafter, referred to as afirst conventional technology) and as “Complementary Pass-transistorLogic” in IEEE Journal of Solid-State Circuits, Vol. sc-25, No. 2, April1990 pp388-pp395 (hereinafter, referred to as a second conventionaltechnology).

Further there has been shown a circuit design method in which a passtransistor circuit is combined with a standard cell system, mentionedabove, in Custom Integrated Circuits Conference 1994 Digest pp603-pp606(hereinafter, referred to as a third conventional technology).

Further, there has also been introduced a design method in which a passtransistor circuit is combined with the standard cell system byutilizing a logical expressing method referred to as “Binary DecisionDiagram” in Proceedings of the 1994 IEICE fall conference (basic andboundary region) of the Institute of Electronics, Information andCommunication Engineers (IEICE), pp64 (hereinafter, referred to as afourth conventional technology).

Further, there has been shown a logical operation circuit cell using apass transistor circuit in Japanese Patent Laid-Open No. 130856/1995(hereinafter, referred to as a fifth conventional technology).

DISCLOSURE OF THE INVENTION

FIG. 10 and FIG. 11 illustrate plane views (a) for explaining layout ofcells of conventional CMOS logical operation circuits and circuitdiagrams thereof (b). Notations p1001 through p1003, n1001 throughn1003, p1101 through p1103 and n1101 through n1103 designatetransistors. According to the layout of a cell of a CMOS logicaloperation circuit which has widely been used in a conventional gatearray or standard cell system shown by FIG. 10 or FIG. 11, it is generalto regularly arrange on a straight line input and output terminalsIn1001 through In1003 and In1101 through In1103 for outputting a signalto outside of the cell. This is because in the case of a CMOS logicaloperation circuit, a portion of a gate can be enlarged on an insulatingfilm (not formed with transistor) present between a first type of afield effect transistor (for example, P-channel MOS) and a second typeof a field effect transistor (for example, N-channel MOS) which are in acomplementary relationship and accordingly, input and output terminals(In1001, In1002, In1003 and Out10 in FIG. 10, In1101, In1102, In1103 andOut11 in FIG. 11) can easily be enlarged therefrom by a conductor layer.

In the meantime, a pass transistor logical operation circuit cell isconstituted by one set or more of pairs of two pass transistors, a gateof each of which responds to a complementary signal and an output signalamplifier. It is a significant feature of a pass transistor logicaloperation circuit cell that a logical circuit portion and an amplifyingcircuit portion are separated in this way. In cell layout of such a passtransistor circuit, when input and output terminals are arranged on astraight line similar to a cell of the conventional CMOS logicaloperation circuit, there poses a problem in which an area efficiency isdeteriorated by a restriction of a design rule concerning a conductorlayer. Accordingly, in a pass transistor logical operation circuit cell,it is not well known how these input and output terminals are to bearranged.

Further, in laying out a pass transistor logical operation circuithaving the above-described constitution, it has not been well known withregard to a problem of how to arrange the output signal amplifier andthe pairs of pass transistors.

Further, in the case of laying out a pass transistor logical operationcircuit cell having the above-described constitution and a CMOS logicaloperation circuit cell on the same chip, it has not been well known withregard to how to arrange a semiconductor region surrounding eachtransistor and having a type reverse to a type of the transistor (forexample, n well in the case of pMOS transistor) in the cell.

Further, it has not been well known with regard to at which portion in alayout inside of a cell as well as outside of a cell, a circuit forgenerating complementary signals provided to respective gates in a pairof two pass transistors in the above-described pass transistor logicaloperation circuit cell, is to be arranged.

Further, in laying out field effect transistors constituting respectivesof a signal polarity inverting circuit for forming complementary signalsprovided to respective gates of a pair of two pass transistors of theabove-described pass transistor logical operation circuit and theabove-described output signal amplifier, it has not been well known withregard to at which positions and in what magnitude relationship they areto be laid out.

Therefore, it is an object of the present invention with regard to acell using a pass transistor circuit, to provide a semiconductorintegrated circuit having a layout arrangement of input and outputterminals, an output signal amplifier, pairs of pass transistors, wellregions and a complementary signal generating circuit capable ofreducing an area, reducing a delay time period and facilitating wiringsoutside of the cell.

In order to achieve the above-described object, a semiconductorintegrated circuit according to the present invention is laid out underthe following thought.

According to the present invention, there is used a cell having aportion constituted by at least one pass transistor circuit for forminga logic and at least one output signal amplifier. In this case, as atypical example of the present invention, an explanation will be givenof a pass transistor logical operation circuit cell in the case in whichthree of pass transistor circuits are present in respect of a singleoutput signal amplifier. As will be shown later in an embodiment of FIG.1 through FIG. 3, each pass transistor circuit includes a first inputnode, a second input node and a third input node, an output node, afield effect transistor of a first type or a second type, a source/drainpath of which is connected between the first input node and the outputnode and a field effect transistor of the first type or the second type,a source/drain path of which is connected between the second input nodeand the output node.

In this case, an output signal amplifier includes a circuit comprisingan input node, an output node, a field effect transistor of a firsttype, a drain/source path of which is connected between the output nodeand first potential and a gate of which responds to the input node and afield effect transistor of a second type, a drain/source path isconnected between the output node and second potential and a gate ofwhich responds to the input node.

The output node of the pass transistor circuit is connected to the inputof the output signal amplifier, an input signal is applied from outsideof the cell to the third input node of the pass transistor circuit andthe input signal from outside cell is applied to at least two of all ofthe first input node and the second input node of the pass transistorcircuit.

The output node of the output signal amplifier operates to output anoutput signal to outside of the cell. One aspect of the thought of thepresent invention is characterized in arranging respective terminals bya conductor layer for drawing an input signal from outside of the celland an output signal to outside of the cell. These are arranged asfollows. That is, when a coordinate system (coordinate axes) isdetermined in a direction of running a supply line of the firstpotential and a supply line of the second potential and a directionorthogonal thereto, the terminals are arranged to include terminal gridpoints disposed at constant intervals in the coordinate system and atleast one-of terminal grid coordinates of the respective terminalsdiffer from terminal grid coordinates arranged with at least two or moreof the terminals other than the above terminals.

According to the above-described semiconductor integrated circuit of thepresent invention, when the coordinate system is disposed in the runningdirection of the potential supply line and the direction orthogonalthereto, input and output terminals are not disposed on the samecoordinates. In other words, the input and output terminals are notaligned in a row, more specifically, these are not aligned in a row in adirection in parallel with the potential supply lines or a boundary line(contour) of the cell. Therefore, by providing an input to the gate ofthe pass transistor and an input to the source/drain of the passtransistor in directions of the coordinate system under the space ruleof the conductor layer, the size of the cell can be reduced with regardto the direction of potential supply lines. In this case, the space rulerefers to a rule of a minimum distance to prevent shortcircuit fromcausing in consideration of a deviation in matching a mask and adeviation in a process fabrication accuracy. Generally, with regard tothe direction orthogonal to the direction of running the potentialsupply lines, the size of the cell is determined commonly in respect ofall of cell groups used in blocks in the chip and accordingly, beingcapable of reducing the size in the direction of the potential supplylines, signifies being capable of reducing the area of the cell.Further, when wirings are provided among cells at an upper layer, thewirings need to draw from the input and output terminals and also inthis case, since the input and output terminals are not disposed on thesame coordinates, the wirings can be drawn from the respective terminalsnot only in the longitudinal direction but also in the transversedirection and there is achieved an advantage of promoting the degree offreedom of wirings.

According to a preferable embodiment of the present invention, when thecoordinate system is determined in the direction orthogonal to thedirection of running the supply line of the first potential and thesupply line of the second potential, a terminal from outside of the cellfor inputting an input signal applied to the third input node of thepass transistor circuit, is arranged to shift to a larger side or asmaller side in view of the coordinate system than a terminal fromoutside of the cell for inputting an input signal applied to the firstinput node and the second input node of the pass transistor circuit.

That is, according to the above-described semiconductor integratedcircuit of the present invention, as will be explained later in theexample of FIG. 1 through FIG. 3, the layout can be conducted reasonablysince a wiring drawn from source/drain of a transistor of the passtransistor circuit to an input terminal and a wiring drawn from gate tothe input terminal do not intersect with each other, whereby the size ofthe cell can be reduced.

Further, according to other preferable embodiment of the presentinvention, when two types of field effect transistors constituting theoutput signal amplifier determine the coordinate system in the directionof running the supply line of the first potential and the supply line ofthe second potential, the transistors are arranged to shift to at leastone of the boundaries of the cell on a side where the coordinate valuesare minimized or on a side where the coordinate values are maximized.

That is, according to the above-described embodiment of the presentinvention, the output signal amplifier is arranged to shift to the cellboundary with regard to the direction of running the potential supplyline and accordingly, even when a plurality of the pass transistorcircuits are present, the output signal amplifier does not hinder wireconnection among the plurality of pass transistor circuits andaccordingly, the cell can reasonably be laid out to a small area.

Further, according to other preferable embodiment of the presentinvention, when a plurality of pass transistors circuit are present, thepass transistor circuits are developed to arrange successively in thedirection of running the supply line of the first potential and thesupply line of the second potential.

According thereto, even when the plurality of pass transistor circuitsare present, a number thereof can be increased flexibly in thedeveloping direction and accordingly, even when the number of the passtransistor circuits is increased, a cell library can regularly be laidout. Thereby, a time period consumed in layout design of the passtransistor logical operation circuit cell can be reduced.

Further, when the plurality of pass transistor circuits are present andthe pass transistor circuits are developed to arrange in the directionof running the supply line of the first potential and the supply line ofthe second potential, a width of a source/drain region of a field effecttransistor constituting the pass transistor circuit in the direction ofrunning the supply line of the first potential and the supply line ofthe second potential is changed in accordance with locations in the samesource/drain region. That is, the width is widened at a portion havingcontact and is narrowed at a portion having no contact.

According to the above-described constitution, the layout can beconducted such that the width of the source/drain region becomes anecessary source/drain width simply for constituting the transistorrather than a width prescribed by source/drain including contact andaccordingly, in applying a space rule between source and drain (referredto as SD space rule), a source/drain region of a contiguous passtransistor circuit is made contiguous to the source/drain region of aportion having no contact by which the size in the running direction ofthe potential supply line can be reduced.

Further, the above-described cell is preferably constituted as follows.When a field effect transistor of a first type and a field effecttransistor of a second type are arranged contiguously to a CMOS logicaloperation circuit cell constituting a logic by coupling them in acomplementary relationship, the following constitution is preferable.

That is, a boundary of a semiconductor region of the second typesurrounding the first type of the field effect transistor constitutingthe CMOS logical operation circuit and a semiconductor region of thefirst type surrounding the second type of the field effect transistor,and a boundary of a semiconductor region of the second type surroundingthe first type of the field effect transistor constituting the passtransistor logical operation circuit and a semiconductor region of thefirst type surrounding the second type of the field effect transistor,are constituted to linearly connect at a connecting portion.

According to the above-described semiconductor integrated circuit of thepresent invention, when the cells are contiguous to each other, the wellboundaries are linearly connected and therefore even when a minimumwidth of a region surrounding a transistor (referred to as a wellminimum width) prescribed by the design rule, is not satisfied by asingle cell, the rule can be satisfied by contiguously arranging aplurality of cells. Accordingly, as a result, the cell area can bereduced. When the embodiment according to the present invention is notused, in the case of arranging a pass transistor logical operationcircuit cell and a CMOS logical operation circuit cell within the sameblock on the same chip, design rule error may be caused, for example, ata location where a single cell which cannot satisfy the rule of the wellminimum width is arranged isolatedly. However, when the cell layoutaccording to the present invention is carried out, the problem isresolved.

Further, as will be explained later in reference to FIG. 4 and FIG. 5,other preferable aspect of the present invention is characterized inthat a boundary (referred to as well boundary) of a semiconductor regionof the second type (referred to as second well) surrounding a fieldeffect transistor of the first type constituting the pass transistorlogical operation circuit and a semiconductor region of the first type(referred to as first well) surrounding the field effect type transistorof the second type, is brought to a side of the first semiconductor orto a side of the second semiconductor at inside of the cell and isarranged to be nonlinear at inside of the cell.

Thereby, regions of the field effect transistors constituting the passtransistor circuit can effectively be provided within the cell. That is,according to the CMOS logical operation circuit cell, normally, atransistor of the first type and a transistor of the second type are ina complementary relationship and their numbers coincide with each other.Therefore, transistors having the same numbers can be laid out on bothsides of a well boundary drawn linearly with no problem. However, in thecase of the pass transistor logical operation circuit cell, a number oftransistors of a type the same as a type of transistors constituting thepass transistor circuit, is larger than a number of transistors of atype different therefrom. Meanwhile, when the boundary of the well islinearly laid out in the cell to be linearly connected to the CMOSlogical operation circuit cell, even when there is constituted adistribution ratio of the first well and the second well suitable forthe CMOS logical operation circuit, it becomes a distribution ratiowhich is not suitable for the pass transistor logical operation circuitcell in which a number of one type is larger than a number of othertype. However, when the above-described embodiment of the presentinvention is used, a region for a transistor constituting the passtransistor circuit can be widened at inside of the cell and accordingly,a difference in the numbers of transistors can successively be realized.

Further, as will be explained in details in reference to FIG. 2, thesemiconductor integrated circuit according to the present invention usesa cell comprising a pass transistor logical operation circuit having atleast one set of pairs each of a pass transistor circuit and an invertercircuit of the signal polarity and at least one output signal amplifier.According to the pass transistor operation circuit of the logicaloperation circuit, there are provided a first input node, a second inputnode and a third input node, an output node, a field effect typetransistor of a first type or a second type, a source/drain path ofwhich is connected between the first input node and the output node anda field effect transistor of the first type or the second type, asource/drain path of which is connected between the second input nodeand the output node.

In this case, the signal polarity inverting circuit includes a circuitcomprising, for example, an input node, an output node, a field effecttype transistor of a first type, a drain/source path of which isconnected between the output node and first potential and a gate ofwhich responds to the input node and a field effect transistor of asecond type, a drain/source path of which is connected between theoutput node and the second potential and a gate of which responds to theinput node.

In this case, the output signal amplifier includes a circuit comprisingan input node, an output node, a field effect transistor of a firsttype, a drain/source path of which is connected between the output nodeand first potential and a gate of which responds to the input node and afield effect transistor of a second type, a drain/source path of whichis connected between the output node and second potential and a gate ofwhich responds to the input node.

Further, the output node of the pass transistor circuit is connected tothe input of the output signal amplifier. In this way, it signifies thatby inserting the signal polarity inverting circuit to inside of thecell, one of input terminals constituting signal connection to outsideof the cell is reduced in respect of a set of a pair of the passtransistor circuits and the signal polarity inverting circuit. Thissignifies that an amount of wiring at outside of the cell is reduced incomparison with the case in which the signal polarity inverting circuitis laid out at outside of the cell and connected therefrom to two of theinput terminals of one pass transistor circuit and wiring is easy tocarry out since a crowdedness of wiring at outside of the cell can bereduced, which is effective. Further, it is preferable that a differencebetween delay times of complementary signals which are to be inputted totwo input terminals of one pass transistor circuit, is small. Because,when the difference between the delay times is large, although theabove-described pass transistor circuits are originally fabricated byassuming that only one of them is made ON, there causes a case in whichboth are made ON or the case both are made OFF. Now, when gate inputs oftwo pass transistors to which the above-described complementary signalsare inputted, are drawn to outside of the cell independently from eachother, it is conceivable that complementary signals are transmitted tothese two inputs by using separate wirings. In such a case, when thereis considerable discrepancy in arrival times of signals by reason inwhich lengths of the separate wirings differ, there can be brought aboutan unpreferable situation in which both are made ON or both are made OFFas mentioned above. However, according to the semiconductor integratedcircuit of the above-described embodiment of the present invention, thesignal polarity inverting circuit is inserted to inside of the cell andaccordingly, the difference between the delay times to the gate inputsof the two pass transistors can be restrained to a small value of only adelay time of the signal polarity inverting circuit at most.

Further, as in later detailed explanation of a constitution in referenceto FIG. 1 and FIG. 2, in a cell comprising a pass transistor logicaloperation circuit having at least a set of pairs each of a passtransistor circuit and a signal polarity inverting circuit and at leastone output signal amplifier, the signal polarity inverting circuit inthe logical operation circuit includes a circuit comprising an inputnode, an output node, a field effect transistor of a first type, adrain/source path of which is connected between the output node andfirst potential and a gate of which responds to the input node and afield effect transistor of a second type, a drain/source path of whichis connected between the output node and second potential and the gateof which responds to the input node.

The output signal amplifier in the logical operation circuit includes acircuit comprising an input node, an output node, a field effecttransistor of a first type, a drain/source path of which is connectedbetween the output node and first potential and a gate of which respondsto the input node and a field effect transistor of a second type, adrain/source path is connected between the output node and secondpotential and a gate of which responds to the input node.

The output node of the pass transistor circuit is connected to the inputof the output signal amplifier, the first type of the field effecttransistor constituting the output signal amplifier is provided with agate width larger than that of the first type of the field effecttransistor constituting the signal polarity inverting circuit and thesecond type of the field effect transistor constituting the outputsignal amplifier is provided with a gate width larger than that of thesecond type of the field effect transistor constituting the signalpolarity inverting circuit.

One aspect of the present invention clearly provides a guiding principlein how to design the channel width of the field effect transistorconstituting the signal polarity inverting circuit. That is, a circuitoutside of the cell driven by the output signal amplifier is not knownat a time point of the layout, in consideration of fanout or a wirecapacity at outside of the cell, there must be assumed a case of drivinga comparatively large load capacity, in contrast thereto, the signalpolarity inverting circuit may only drive the gate of the passtransistor circuit at inside of the cell. When the channel width of thefield effect transistor constituting the signal polarity invertingcircuit is made larger than the channel width of the field effecttransistor constituting the output signal amplifier, regardless of therelationship of the load capacity, large capacity is driven by a smalltransistor and small load capacity is driven by large capacity, as aresult, there poses a problem in which a delay time period of a total isincreased. In contrast thereto, by conducting layout such that thechannel width of the field effect transistor constituting the signalpolarity inverting circuit is made smaller than the channel width of thefield effect transistor constituting the output signal amplifier, therespectives can be constituted by transistor sizes pertinent to drivenload capacities and the delay time period can be reduced.

Further, according to a preferable embodiment of the present invention,the output node of the pass transistor circuit is connected to the inputof the output signal amplifier and the field effect transistorconstituting the pass transistor circuit, is arranged between fieldeffect transistors of a first type and a second type constituting thesignal polarity inverting circuit with regard to a direction orthogonalto a direction of running a supply line of the first potential and asupply line of the second potential.

By arranging them in this way, the space rule in view of layout betweenthe source/drain region and the semiconductor region (well or substrate)surrounding thereof is not adopted unnecessarily, wire connection amongpass transistor circuits and installation of an electricity feeding lineto the source of the signal polarity inverting circuit can reasonably becarried out and accordingly, as a result, the cell area can be reduced.

Further, preferably, the output signal amplifier in the logicaloperation circuit includes a circuit comprising an input node, an outputnode, a first field effect transistor of a first type, a drain/sourcepath of which is connected between the output node and first potentialand a gate of which responds to the input node, a second field effecttransistor of a second type, a drain/source path of which is connectedbetween the output node and second potential and a gate of whichresponds to the input node and a third field effect transistor of thefirst type, a drain/source path of which is connected between the inputnode and the first potential and a gate of which responds to the outputnode. Further, according to the output signal amplifier, wire connectionfrom the drain of the third field effect transistor to the gates of thefirst field effect transistor and the second field effect transistor isrealized by passing the wire connection below a first potential supplyline by using a material for the gate terminal of the transistor.

In this way, by using the gate material as a wiring, the portion belowthe potential supply line can effectively be utilized and accordingly,there can be resolved a problem in which wiring operation becomesdifficult which is caused when wirings at vicinities of the first fieldeffect transistor and the third field effect transistor of the outputsignal amplifier are crowded.

Other objects and novel characteristics of the present invention willbecome apparent by the following embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout diagram of a logical operation circuit cell accordingto an embodiment of the present invention.

FIG. 2 is a circuit diagram of the logical operation circuit cellaccording to the embodiment of the present invention.

FIG. 3 is a layout diagram of the logical operation circuit cellaccording to the embodiment of the present invention.

FIG. 4 is a layout diagram of a logical operation circuit cell accordingto an embodiment of the present invention.

FIG. 5 is a circuit diagram of the logical operation circuit cellaccording to the embodiment of the present invention.

FIG. 6 is a layout diagram of the logical operation circuit cellaccording to the embodiment of the present invention.

FIG. 7 is a layout diagram arranging a plurality of the logicaloperation circuit cells according to the embodiment of the presentinvention.

FIG. 8 is a layout diagram arranging and connecting a plurality of thelogical operation circuit cells according to the embodiment of thepresent invention.

FIG. 9 illustrates sectional views of the logical operation circuit cellaccording to the embodiment of the present invention.

FIG. 10 is a layout diagram of a conventional CMOS logical operationcircuit (3 inputs NAND).

FIG. 11 is a layout diagram of a conventional CMOS logical operationcircuit (3 inputs NOR).

FIG. 12 is a layout diagram arranging the logical operation circuitcells according to the embodiment of the present invention by invertingthe cells horizontally.

FIG. 13 is a layout diagram arranging the logical operation circuitcells according to the embodiment of the present invention by invertingthe cells vertically.

FIG. 14 is a layout diagram arranging logical operation circuit cellsaccording to the embodiment of the present invention by inverting thecells vertically.

BEST MODE FOR CARRYING OUT THE INVENTION

An explanation will be given of embodiments according to the presentinvention in reference to the drawings as follows.

FIG. 1 illustrates layout of a pass transistor logical operation circuitcell when three of pass transistor circuits are present in respect ofone output signal amplifier.

FIG. 2 illustrates a circuit in correspondence with FIG. 1. Basically,there are provided a logical circuit portion (PC21 through PC23)constituted by nMOS's, input amplifiers (inverters 201 through 203)constituted by CMOS's and an output amplifier (BC21). First, adescription will be given of correspondence between layout and circuit.

FIG. 3 shows correspondence between FIG. 1 and FIG. 2. Although layoutof FIG. 3 is the same as that of FIG. 1, the layout shows transistorsand input and output terminals along with numerals. Correspondencebetween these and transistors and input and output terminals in FIG. 2is as follows.

p21 of FIG. 2 corresponds to 301 of FIG. 3, n21 of FIG. 2 corresponds to302 of FIG. 3, n22 of FIG. 2 corresponds to 303 of FIG. 3, n23 of FIG. 2corresponds to 304 of FIG. 3, n24 of FIG. 2 corresponds to 307 of FIG.3, n25 of FIG. 2 corresponds to 308 of FIG. 3, n26 of FIG. 2 correspondsto 311 of FIG. 3, n27 of FIG. 2 corresponds to 312 of FIG. 3, Out2 ofFIG. 2 corresponds to 316 of FIG. 3, In21 of FIG. 2 corresponds to 317of FIG. 3, In 22 of FIG. 2 corresponds to 318 of FIG. 3, In23 of FIG. 2corresponds to 319 of FIG. 3, In24 of FIG. 2 corresponds to 320 of FIG.3, In25 of FIG. 2 corresponds to 321 of FIG. 3, In26 of FIG. 2corresponds to 322 of FIG. 3 and In27 of FIG. 2 corresponds to 323 ofFIG. 3.

Further, the inverter 201 is constituted by transistors 305 and 306 ofFIG. 3, The inverter 203 of FIG. 2 is constituted by transistors 313 and314 of FIG. 3, and the inverter 202 of FIG. 2 is constituted bytransistors 309 and 310 of FIG. 3 and p22 of FIG. 2 corresponds to 315of FIG. 3.

The semiconductor integrated circuit according to the present inventionis laid out by the following thought. According to the presentinvention, there is used a cell (FIG. 1 and FIG. 2) comprising a logicaloperation circuit having at least one of pass transistor circuits (PC21,PC22, PC23 of FIG. 2) and at least one output signal amplifier (PC21 ofFIG. 2). In this case, as shown by FIG. 1 through FIG. 3, a passtransistor circuit in the logical operation circuit (PC21, PC22, PC23 ofFIG. 2) includes a first input node, a second input node and a thirdinput node, an output node, a field effect transistor of a first type ora second type (in FIG. 2, n22, n24 and n26), a source/drain path ofwhich is connected between the first input node and the output node anda field effect transistor of the first type or the second type (in FIG.2, n23, n25 and n27 of n type), a source/drain path of which isconnected between the second input and the output node.

The output signal amplifier (BC21 of FIG. 2) in the logical operationcircuit, includes an input node, an output node, a field effecttransistor of a first type (in FIG. 2, p21 of p type), a source/drainpath is connected between the output node and first potential and a gateof which responds to the input node and a field effect transistor of asecond type (in FIG. 2, n21 of n type), a drain/source path is connectedbetween the output node and second potential and a gate of whichresponds to the input node.

Further, the output node of the pass transistor circuit is connected tothe input of the output signal amplifier, an input signal from outsideof the cell is applied to the third input node of the pass transistorcircuit and input signals from outside of the cell are applied to atleast two of all of the first input nodes and the second input nodes ofthe pass transistor circuits (at least two of In21, In22, In23, In24,In25, In26 and In27 of FIG. 2).

The output node (Out2 of FIG. 2) of the output signal amplifier operatesto output an output signal to outside of the cell. Respective terminalsby a conductor layer (for example, 1-th layer of metal wiring) fordrawing the input signals from outside of the cell and the output signalto outside of the cell, are arranged as follows. That is, when acoordinate system is determined in a direction of running a firstpotential supply line and a second potential supply line and a directionorthogonal thereto, the respective terminals are arranged to includeterminal grid points disposed at constant intervals in the coordinatesystem, in which terminal grid coordinates of at least one of therespective terminals differ from terminal grid coordinates where atleast two or more of terminals are arranged (101, 102, 103 etc of FIG.1).

According to the semiconductor integrated circuit of the embodiment ofthe present invention as mentioned above, when a coordinate system isset in a direction of running the power supply lines and a directionorthogonal thereto, input and output terminals are not disposed on thesame coordinates. Therefore, for example, by providing the space rule ofthe conductor layer in respect of input to a gate of a pass transistorand input to a source and a drain of the pass transistor in a direction(vertical direction in FIG. 1) of the above-described coordinate system,the size of the cell can be reduced in the direction of the potentialsupply lines (horizontal direction in FIG. 1). Generally, with regard tothe direction of running the potential supply lines and the lineorthogonal thereto (vertical direction in FIG. 1), the size of the cellis determined commonly in respect of all of cell groups used in blocksin a chip and accordingly, being capable of reducing the size in thedirection of the potential supply lines (horizontal direction in FIG.1), signifies being able to reduce the area of the cell. Further, whenwirings are provided among cells at an upper layer, the wirings need todraw from the input and output terminals and also in this case, theinput and output terminals are not disposed on the same coordinates andaccordingly, the wirings can be drawn from the respective terminals notonly in the vertical direction but also in the horizontal direction andthere is achieved an advantage in which the degree of freedom of wiringis promoted.

Further, a terminal (which corresponds to 101 of FIG. 1, In23 of FIG. 2)from outside of the cell for an input signal applied to the third inputnode of the pass transistor circuit, is arranged to shift to a largerside or a smaller side in the coordinate system rather than terminals(which corresponds to 102 or 103 of FIG. 1, In26 and In27 of FIG. 2)from outside of the cell for input signals applied to the first inputnode and the second input node of the pass transistor circuit.

According to such a semiconductor integrated circuit, a wire which pullsthe signal out from source/drain of a transistor in the pass transistorcircuit (which corresponds to, for example, 108 of FIG. 1, PC23 of FIG.2) to an input terminal (102 or 103) and a wire drawn from gate to aninput terminal (101 of FIG. 1) do not intersect with each other andtherefore, layout can be carried out reasonably by which the size of thecell can be reduced.

Further, the embodiment is characterized in that two types of fieldeffect transistors (104, 105 of FIG. 1) constituting the output signalamplifier are arranged to shift to at least one of a boundary of thecell on a side of smallest coordinate values and a boundary of the cellon a side of largest coordinate values (left side in FIG. 1) when acoordinate system is determined in the direction of running the firstpotential supply line and the second potential supply line.

According to the above-described semiconductor integrated circuit inaccordance with the embodiment of the present invention, the outputsignal amplifier is arranged to shift to the cell boundary with regardto the running direction of the potential supply line (horizontaldirection of FIG. 1) (104, 105 of FIG. 1) and therefore, even when aplurality of the above-described pass transistor circuits are present(PC21, PC22, PC23 of FIG. 2), wire connection among the plurality ofpass transistors is not hampered and therefore, the cell can be laid outreasonably in a small area.

Further, according to the embodiment, when the plurality of passtransistor circuits are present (for example, PC21, PC22, PC23 of FIG.2), the pass transistor circuits are developed to arrange in thedirection of running the first potential supply line and the secondpotential supply line. In FIG. 1, the pass transistor circuits aredeveloped to arrange in an order of 106, 107 and 108.

According to the above-described semiconductor integrated circuit inaccordance with the embodiment of the present invention, the outputsignal amplifier is arranged at an end of the cell (104, 105 of FIG. 1),even when a plurality of pass transistor circuits are present (forexample, PC21, PC22, PC23 of FIG. 2), a number thereof can flexibly beincreased in the developing direction and therefore, even when thenumber of the pass transistor circuits is increased, the cell librarycan regularly be laid out. Thereby, a time period consumed in layoutdesign of a pass transistor logical operation circuit cell can bereduced.

Further, according to the embodiment, a width of a source/drain regionof a field effect transistor constituting a pass transistor circuit(PC22 of FIG. 2 and 107 of FIG. 1 correspond thereto) in the directionof running the first potential supply line and the second potentialsupply line (leftist side of source/drain region in 107 of FIG. 1) ischanged depending on locations in the same source/drain region. That is,in FIG. 1, the width is widened at an upper portion having contact andis narrowed at a lower portion having no contact.

In this way, the width of the source/drain region can be laid out by asource/drain width necessary for simply constituting a transistor ratherthan a width prescribed by source and drain and therefore, in applyingthe space rule (referred to as SD space rule between source and drain)by making a source/drain region of a contiguous pass transistor circuitto be contiguous to a source/drain region of a portion having nocontact, the size in a direction of running of a potential supply line(horizontal direction in FIG. 1) can be reduced.

According to the embodiment, at inside of the cell, there are a pair ofat least one set of pass transistor circuits (PC21, PC22, PC23 of FIG.2) and a signal polarity inverting circuit (201, 202, 203 of FIG. 2) andat least one output signal amplifier (BC21 of FIG. 2). The signalpolarity inverting circuit (201, 202, 203) includes a circuit comprisingan input node, an output node, a field effect transistor of a firsttype, a drain/source path of which is connected between the output nodeand first potential and a gate of which responds to the input node and afield effect transistor of a second type, a drain/source path of whichis connected between the output node and second potential and a gate ofwhich responds to the input node.

In this way, by inserting the signal polarity inverting circuit toinside of the cell, a number of input terminals constituting signalconnections to outside of the cell is reduced by one per a pair of oneset of a pass transistor circuit and a signal polarity invertingcircuit. This signifies that an amount of wiring at outside of the cellis reduced in comparison with the case in which the signal polarityinverting circuit is laid out at outside of the cell and connectedtherefrom to two input terminals of one pass transistor circuit, thedegree of crowdedness of wirings at outside of the cell can be reducedand accordingly, wiring operation is easy to carry out. Further, it ispreferable that a difference between delay time periods is small incomplementary signals to be inputted to two input terminals of one passtransistor circuit. Because when the difference between the delay timeperiods is large although the above-described pass transistor circuit isoriginally fabricated by assuming that either one of them is made ON,there causes a case in which the both are made ON or the case in whichboth are made OFF. Now, when gate inputs of two pass transistors towhich the above-described complementary signals are inputted, are drawnto outside of the cell independently from each other, it is conceivablethat the complementary signals are transmitted to these two inputs byusing separate wirings. In such a case, when there is a significantdiscrepancy between arrival times of the signals owing to the reasonthat lengths of the separate wirings differ, there can be brought aboutan unpreferable situation in which both are made ON or both are made OFFas mentioned above. However, according to the embodiment of the presentinvention, described above, the signal polarity inverting circuit isinserted to inside of the cell and accordingly, the difference betweenthe delay time periods to the gate inputs of the two pass transistorscan be restrained small only to a delay time period of the signalpolarity inverting circuit at most.

In this case, the first type field effect transistor 104 constitutingthe output signal amplifier, is provided with a gate width which islarger than that of a first type field effect transistor 109constituting the signal polarity inverting circuit. Further, the secondtype field effect transistor 105 constituting the output signalamplifier, is characterized in having a gate width which is larger thanthat of a second type field effect transistor 110 constituting thesignal polarity inverting circuit. The gate width can be defined as, forexample, a length in a length direction of a polysilicon layer at aportion thereof where a diffused layer and the polysilicon layerconstituting a gate electrode overlap. As a characteristic, gain of theoutput signal amplifier is made larger than gain of the signal polarityinverting circuit.

That is, a circuit outside of the cell which is driven by the outputsignal amplifier is not known at a time point of laying out the cell, inconsideration of fan-out and a capacity of wiring at the outsideportion, there must be assumed a case of driving comparatively largeload capacity, in contrast thereto, the signal polarity invertingcircuit may only drive the gate of the pass transistor circuit at insideof the cell. When the channel width of the field effect transistorconstituting the signal polarity inverting circuit is made larger thanthe channel width of the field effect transistor constituting the outputsignal amplifier, large capacity is driven by a small transistor andsmall load capacity is driven by large capacity regardless of theabove-described relationship of load capacity, as a result, there posesa problem in which a delay time period of a total is increased. Incontrast thereto, the channel width of the field effect transistorconstituting the signal polarity inverting circuit is laid out to besmaller than the channel width of the field effect transistorconstituting the output signal amplifier by which the respectives can beprovided with transistor sizes pertinent for load capacity and the delaytime period can be reduced.

According to the embodiment, the output node of the pass transistorcircuit is connected to the input of the output signal amplifier, afield effect transistor (111) constituting the pass transistor circuit(PC21 of FIG. 2), is arranged between the first type and the second typefield effect transistors (109 and 110) constituting the signal polarityinverting circuit in a direction orthogonal to the direction of runningthe first potential supply line and the second potential supply line.

By arranging them in this way, the space rule in view of layout betweena source/drain region and a semiconductor region (well or a substrate)surrounding thereof is not unnecessarily adopted, connection among thepass transistor circuits and installation of an electricity feeding lineto the source of the signal polarity inverting circuit can be conductedreasonably and therefore, as a result, the cell area can be reduced.Now, consider a case in which when the field effect transistor (110)constituting the pass transistor circuit is of the second type, thetransistor is arranged not between the two transistors constituting thesignal polarity inverting circuits but thereabove or therebelow. First,consider as case in which the transistor is arranged thereabove. Thissignifies that in the first place, transistors of a second type arearranged above and below a transistor of a first type and accordingly,semiconductor regions surrounding the transistor need to provideseparately to the respective two transistors of the second type.Generally, a space rule on a layout between a source/drain region of atransistor and a semiconductor region (well or a substrate) surroundingthereof (now, this is referred to as a WELL-SD region space rule)becomes significantly larger than the minimum rule for the layout.Therefore, when arranged in this way, at least two of the WELL-SDregions are needed between the transistor constituting the passtransistor and the first type transistor of the signal polarityinverting circuit and further two of the WELL-SD region space rule areneeded between the first type transistor of the signal polarityinverting circuit and the second transistor. Thereby, there poses aproblem in which the size of the cell in the vertical direction isincreased. Next, consider a case in which it is arranged therebelow. Inthis case, the second type transistor constituting the pass transistorcircuit and the second type transistor constituting the signal polarityinverting circuit can be realized in the same semiconductor region (wellor a substrate) and accordingly, only two of the WELL-SD region spacerule are needed between the first type transistor and the second typetransistor of the signal polarity inverting circuit, which is morepreferable than in the case of arranging it thereabove. However, in thiscase, a wiring for feeding electricity to the source of the second typetransistor constituting the signal polarity inverting circuit (referredto as source electricity feeding wiring) needs to draw from the secondpotential supply line to above the transistor constituting the passtransistor circuit. However, when considering a case in which aplurality of pass transistor circuits are present and wire connectionneeds to carry out among them. In order to prevent the connected wiring(for example, 112 in FIG. 1) from being intersected with theabove-described source electricity feeding wiring (for example, 113 ofFIG. 1), the wire connection needs to carry out among the passtransistor circuits by drawing the wiring above the second typetransistor constituting the signal polarity inverting circuit or eitherof the two wirings needs to connect in a wiring layer at one upperlayer. In the former case, the wiring needs to draw significantly andtherefore, the wiring is difficult and the cell area is increased.Further, in the latter case, generally, the wiring in an upper layer isused in wiring outside of the cell and accordingly, when the wiring isused at inside of the cell, the degree of freedom of wiring outside ofthe cell is significantly deteriorated and accordingly, it is notpreferable as well. In the meantime, according to the above-describedembodiment of the present invention, either of these problems can beresolved and accordingly, the embodiment is preferable.

When a further detailed explanation is given to the output signalamplifier in the logical operation circuit in reference to FIG. 1, thereis provided a circuit comprising an input node, an output node, thefirst field effect transistor 104 of the first type, a drain/source pathof which is connected between the output node and first potential and agate of which responds to the input node, the second field effecttransistor 105 of the second type, a drain/source path of which isconnected between the output node and the second potential and a gate ofwhich responds to the input node and a third field effect transistor 114of the first type, a drain/source path of which is connected between theinput node and first potential and a gate of which responds to theoutput node. According to the output signal amplifier, wire connectionfrom a drain of the third field effect transistor to the gates of thefirst field effect transistor and the second field effect transistor, iscarried out by 115 passing below the first potential supply line byusing a gate material.

By using the gate material as wiring in this way, the lower side of thepotential supply line can effectively be utilized and accordingly, therecan be resolved a problem in which wiring operation becomes difficultwhen wiring at the vicinities of the first field effect transistor andthe third field effect transistor of the output signal amplifier iscrowded.

An explanation will be given of other embodiment of the presentinvention in reference to FIG. 4 and FIG. 5. FIG. 4 shows layout of apass transistor logical operation circuit cell when five of passtransistor circuits are present for one output signal amplifier. FIG. 5shows a circuit in correspondence with FIG. 4. First, correspondencebetween layout and circuits will be given.

Correspondence between FIG. 4 and FIG. 5 is shown by FIG. 6. Althoughlayout of FIG. 6 is the same as that of FIG. 4, the layout showstransistors and input and output terminals along with numerals.Correspondence between these and transistors and input and outputterminals of FIG. 5 is as follows.

p51 of FIG. 5 corresponds to 601 of FIG. 6, p52 of FIG. 5 corresponds to602 of FIG. 6, n51 of FIG. 5 corresponds to 603 of FIG. 6, n52 of FIG. 5corresponds to 604 of FIG. 6, n53 of FIG. 5 corresponds to 605 of FIG.6, n54 of FIG. 5 corresponds to 606 of FIG. 6, n55 of FIG. 5 correspondsto 607 of FIG. 6, n56 of FIG. 5 corresponds to 608 of FIG. 6, n57 ofFIG. 5 corresponds to 609 of FIG. 6, n58 of FIG. 5 corresponds to 610 ofFIG. 6, n59 of FIG. 5 corresponds to 611 of FIG. 6, n510 of FIG. 5corresponds to 612 of FIG. 6, n511 of FIG. 5 corresponds to 613 of FIG.6, 501 of FIG. 5 corresponds to 614 and 615 of FIG. 6, 502 of FIG. 5corresponds to 616 and 617 of FIG. 6, 503 of FIG. 5 corresponds to 618and 619 of FIG. 6, 504 of FIG. 5 corresponds to 620 and 621 of FIG. 6,505 of FIG. 5 corresponds to 622 and 623 of FIG. 6, Out5 of FIG. 5corresponds to 624 of FIG. 6, In51 of FIG. 5 corresponds to 625 of FIG.6, In52 of FIG. 5 corresponds to 626 of FIG. 6, In53 of FIG. 5corresponds to 627 of FIG. 7, In54 of FIG. 5 corresponds to 628 of FIG.6, In55 of FIG. 5 corresponds to 629 of FIG. 6, In56 of FIG. 5corresponds to 630 of FIG. 6, In57 of FIG. 5 corresponds to 631 of FIG.6, In58 of FIG. 5 corresponds to 632 of FIG. 6, In59 of FIG. 5corresponds to 633 of FIG. 6, In510 of FIG. 5 corresponds to 634 of FIG.6 and In511 of FIG. 5 corresponds to 635 of FIG. 6.

According to the embodiment, there is provided a cell (FIG. 4, FIG. 5and 705 of FIG. 7) comprising a logical operation circuit having atleast one pass transistor circuit (PC51 of FIG. 5) and at least oneoutput signal amplifier (BC51 of FIG. 5).

The pass transistor circuit (PC51, PC52, PC53 of FIG. 5) in the logicaloperation circuit includes a first input node, a second input node and athird input node, an output node, a field effect transistor of a firsttype or a second type (n52, n54, n56 of FIG. 5), a source/drain path ofwhich is connected between the first node and the output node and afield effect transistor of the first type or the second type (n53, n55,57 of FIG. 2), a source/drain path of which is connected between thesecond input node and the output node.

The output signal amplifier (BC51 of FIG. 5) in the logical operationcircuit includes a circuit comprising an input node, an output node, afield effect transistor of a first type (p51 of FIG. 5), a drain/sourcepath of which is connected between the output node and first potentialand a gate of which responds to the input node and a field effecttransistor of a second type (n51 of FIG. 5), a drain/source path ofwhich is connected between the output node and the second potential anda gate of which responds to the input node.

The output node of the pass transistor circuit is connected to the inputof the output signal amplifier. In this case, each cell is assumed toarrange contiguous to a CMOS logical operation circuit cell constitutinga logic by connecting a first type field effect transistor and a secondtype field effect transistor in a complementary relationship (refer toarrangement of 704 and 705 of FIG. 7 explained below).

A boundary (referred to as well boundary) between a semiconductor regionof a second type (referred to as second well) surrounding a field effecttransistor of a first type constituting the transistor logical operationcircuit and a semiconductor region of a first type (referred to as firstwell) surrounding a field effect transistor of a second type, is broughtinto a first semiconductor side or a second semiconductor side at insideof the cell (401 of FIG. 4) and is arranged nonlinearly at inside of thecell.

According to the above-described semiconductor integrated circuit inaccordance with the embodiment of the present invention, a region of afield effect transistor constituting a pass transistor circuit caneffectively be provided at inside of the cell. That is, according to aCMOS logical operation circuit cell, normally, a transistor of a firsttype and a transistor of a second type are brought into a complementaryrelationship and numbers of these coincide with each other. Accordingly,transistors having the same numbers can respectively be laid out with noproblem on both sides of a well boundary drawn linearly. However, in thecase of a pass transistor logical operation circuit cell, a number oftransistors of a type the same as that of transistors constituting thepass transistor circuit becomes larger than a number of transistorshaving a type different therefrom. Meanwhile, when the cell boundary islaid out linearly even at inside of the cell to be linearly connected tothe CMOS logical operation circuit cell having a contiguous boundary,even if there is constituted a distribution ratio of a first well and asecond well suitable for the CMOS logical operation circuit cell, itbecomes a distribution ratio which is not suitable for the passtransistor logical operation circuit cell in which one type oftransistors are more than other type of transistors. However, when theabove-described embodiment of the present invention is used, there isprovided a wide region for transistors constituting the pass transistorcircuit at inside of the cell and accordingly, a difference in thenumber of transistors can successively be realized.

According to the layout of the cell of the embodiment (FIG. 4), theinput and output terminals (402 through 406) are not arranged to includethe same terminal grid coordinates in respect of the vertical directionof the drawings. According to the CMOS logical operation circuit cell,even when all of inputs and outputs include the same terminal gridcoordinates in the vertical direction (terminal grid coordinates in thehorizontal direction may naturally differ), there poses no problem sincea number of input and output terminals per cell is small (refer to FIG.10), however, in the case of the pass transistor logical operationcircuit cell, a number of input and output terminals per cell is largerthan that of the CMOS logical operation circuit cell which poses aproblem. Now, when four terminals of the input terminals 402, 403, 404and 405 are used to arrange to include the same terminal gridcoordinates in respect of the vertical direction of the drawing, a spacerule at least prescribed by a design rule of a wiring layer surroundingthe terminals, is needed among them and therefore, at least three of thespace rules are needed in the horizontal direction. However, when thereare set terminal grid coordinates which are different in the verticaldirection as in 402 and 404 and 403 and 405 as in the embodiment, inarranging four of these input terminals, only one of the above-describedspace rule is sufficient. Accordingly, the cell size in the horizontaldirection can be reduced.

Further, according to the semiconductor integrated circuit of theembodiment, the input terminal (404, 405 of FIG. 4) to the source/drainregion of the transistor constituting the pass transistor circuit isarranged on the lower side of the drawing than the input terminal (402,403 of FIG. 4) to the gate. By arranging in this way, a wiring drawnfrom the source/drain of the transistor constituting the pass transistorcircuit and a wiring drawn from the gate do not intersect with eachother and can reasonably be laid out and therefore, the cell area can bereduced.

Further, according to the semiconductor integrated circuit of theembodiment, the output signal amplifier (407 and 408 of FIG. 4) isarranged at an end of the cell (in respect of the horizontal direction).In the case of the embodiment in which five of the pass transistorcircuits are present in respect of the single cell, as shown by thecircuit of FIG. 5, wire connection among the five pass transistors isincreased. In such a case, when the output signal amplifier is notarranged at an end of the cell but is arranged at the center of thecell, or arranged within a portion where the five pass transistorcircuits are arranged, a wiring (409) in the output signal amplifier anda wiring (410) between the pass transistor circuits, are liable tointersect with each other and the wiring operation becomes difficult.However, it is known that according to the embodiment, such a problem isavoided.

Further, according to the semiconductor integrated circuit of theembodiment, the output signal amplifier is arranged at a right end andfive of the pass transistor circuits are arranged to develop on a rightside thereof (411, 412, 413, 414, 415) In considering this case in viewof the case of FIG. 1 where three of the pass transistor circuits arepresent, it is known that while substantially a similar arrangement isprovided to the output signal amplifier on the left side and the threepass transistor circuits are arranged to the right, two pass transistorcircuits are further added to the right. By constituting such anarrangement, even when a plurality of the pass transistor circuits arepresent, in view of layout, additional portions may be laid out to acell having pass transistor circuits of a smaller number. Accordingly, atime period required for the cell layout can significantly be reduced.

Further, according to the semiconductor integrated circuit of theembodiment, a width of the source/drain region of the field effecttransistor constituting the pass transistor circuit in the direction ofrunning a supply line of the first potential and a supply line of thesecond potential (for example, source/drain region on the left side of412), is changed depending on locations in the same source/drain region.Thereby, the above source/drain region can be made contiguous to thesource/drain region of a contiguous pass transistor circuit (asource/drain region on the right of 411) at a portion having no contactwhereby a size in the running direction of the potential supply line isreduced.

Further, according to the semiconductor integrated circuit of theembodiment, as mentioned above, the boundary (well boundary, 401)between the semiconductor region (referred to as a second type well)surrounding the first type of the transistor and the semiconductorregion (referred to as a first type well) surrounding the second type ofthe transistor, is bent to break nonlinearly at inside of the cell. Thatis, in this case, a region of the first type well is larger than aregion of the second type well. Now, according to the cell, there areseven of the first type transistors and twelve of the second typetransistors and a number of the second type transistors is larger thanthat of the first type transistors. According to the embodiment of thepresent invention, by widening the first type well region, a region oflaying out the second type transistors can widely be provided. Further,a boundary portion in respect with a contiguous cell coincides with awell boundary line provided to the CMOS logical cell and a rule for theminimum width of well in contiguously arranging a plurality of cells canbe satisfied with no problem.

Further, according to the semiconductor integrated circuit of theembodiment, a signal polarity inverting circuit is inserted into theinside of the cell in pair with the pass transistor circuit. That is, inFIG. 4, there is at inside of the cell a signal polarity invertingcircuit (constituted by 416 and 417) for forming a complementary signalto a gate of one transistor thereof. The advantage of constituting sucha mode has already been described.

Further, according to the semiconductor integrated circuit of theembodiment, although the signal polarity inverting circuit is insertedinto the cell in pair with the pass transistor circuit, a channel widthof a transistor constituting the output signal amplifier is larger thana channel width of a transistor constituting the signal polarityinverting circuit. That is, in FIG. 4, with regard to the first typefield effect transistor, the width of 407 is larger than that of 416 andwith regard to the second type field effect transistor, the width of 408is larger than that of 417. The advantage of constituting the mode hasalready been described.

Further, according to the semiconductor integrated circuit of theembodiment, the signal polarity inverting circuit is inserted into thecell in pair with the pass transistor circuit and a transistor (418)constituting the pass transistor circuit is arranged between the firsttype transistor (416) and the second type transistor (417) constitutingthe signal polarity inverting circuit. The advantage of constituting themode has already been described.

An explanation will be given of other embodiment in reference to FIG. 7.In FIG. 7, there are provided cells 701, 703 and 705 comprising logicaloperation circuits each having at least one pass transistor circuit (forexample, may be similar to circuits shown by PC21, PC22, PC23 of FIG. 2)and at least one output signal amplifier (for example, may be similar tothe circuit shown by BC21 of FIG. 2). An output node of the passtransistor circuit is connected to the input of the output signalamplifier similar to the example of FIG. 2.

FIG. 7 shows a behavior of arranging the pass transistor logicaloperation circuit cells 701, 703 and 705 contiguous to generally usedCMOS logical operation circuit cells. Portions of connecting wells 707,710, 712 and 713 of the pass transistor logical operation circuit cellsand well boundaries of the CMOS logical operation circuit cells 708,709, 711 and 714 become linear.

As shown by FIG. 7, the cells 701 and 703 or the cell 705 are arrangedcontiguous to a CMOS logical operation circuit cell 702 or cells 704 and706 each constituting a logic by connecting a first type of a fieldeffect transistor and a second type of a field effect transistor in acomplementary relationship. In this case, linear connection is realizedat portions of connecting boundaries 708, 709, 711 and 714 ofsemiconductor regions of the second type surrounding the first type ofthe field effect transistor constituting the CMOS logical operationcircuit and semiconductor regions of the first type surrounding thefield effect transistor of the second type, and boundaries 707, 710, 712and 713 (referred to as well boundaries) of semiconductor regions of thesecond type surrounding the first type of the field effect transistorconstituting the pass transistor logical operation circuit andsemiconductor regions of the first type surrounding the second type ofthe field effect transistor.

According to the example, when cells are contiguous to each other, thewell boundaries are linearly connected and accordingly, even in the casein which a minimum width of a region surrounding a transistor prescribedby a design rule (referred to as rule for the minimum width of well) isnot satisfied only by a single cell, the rule can be satisfied bycontiguously arranging a plurality of the cells. Accordingly, as aresult, the cell area can be reduced. When the embodiment according tothe present invention is not used, in arranging contiguously a passtransistor logical operation circuit and a CMOS logical operationcircuit cell in the same block on the same chip, design rule error iscaused at a particular location (location where only one of a cell whichcannot satisfy the above-described rule for the minimum width of well isisolatedly arranged). However, when the cell layout according to thepresent invention is carried out, the problem is resolved.

FIG. 8 shows a behavior in which the pass transistor logical operationcircuit cells according to the present invention are arranged contiguousto generally used CMOS logical operation circuit cells and these cellsare connected by using an upper layer of a wiring layer. An input isdesignated by In and an output is designated by Out. In the drawing, byoverlapping four of cross portions on FIG. 7, illustrated above, arelationship between a lower layer and the upper layer becomes apparent.In this case, there is shown an example in which a second layer is usedin wirings in the vertical direction and a third layer is used inwirings in the horizontal direction. In this case, while wirings of theCMOS logical operation circuit cells are drawn only in the verticaldirection, in the case of the pass transistor logical operation circuitcells, the wirings are drawn in the horizontal direction.

FIG. 9(a) shows a pass transistor logical operation circuit cell thesame as that in FIG. 1. FIG. 9(b) and FIG. 9(c) schematically representsectional views when the cell is cut along a line designated by 901.FIG. 9(b) shows a case in which a second layer of a wiring is not drawnto an output terminal 901 of FIG. 9(a) and FIG. 9(c) shows a case inwhich the wiring is drawn thereto. 903 of FIG. 9(c) shows drawing of awiring at a second layer.

FIG. 12 shows a case in which a pass transistor logical operationcircuit cell 1201 and 1202 where the pass transistor logical operationcircuit cell 1201 is inverted in the horizontal direction, arecontiguously arranged and connected. Although according to theembodiment, 1202 is produced by inverting 1201 in the horizontaldirection, a cell to be inverted may naturally be other pass transistorlogical operation circuit cell or a CMOS operation circuit cell.

FIG. 13 shows a case in which a pass transistor logical operationcircuit cell 1301 and 1302 produced by inverting the pass transistorlogical operation circuit cell in the vertical direction, arecontiguously arranged and connected. Although according to theembodiment, 1302 is produced by inverting 1301 in the verticaldirection, a cell to be inverted may naturally be other pass transistorlogical operation circuit cell or a CMOS logical operation circuit cell.

FIG. 14 shows a case in which a pass transistor logical operationcircuit cell 1401 and 1402 produced by inverting the pass transistorlogical operation circuit cell in the vertical direction, arecontiguously arranged and connected. However, what differs from theembodiment of FIG. 13 resides in arranging to overlap electricityfeeding portions for latch up measure to semiconductor regions (well)surrounding transistors of upper and lower two cells simultaneous withthe vertical inversion. In this way, there is achieved an advantage ofcapable of making the cell area smaller than that in the case of FIG.13.

Although a detailed explanation has been given of the embodimentsaccording to the present invention which have been carried out by theinventors, the present invention is not limited to the above-describedspecific embodiments but may naturally be modified variously within therange of the technical thought.

For example, the field effect transistor of the pass transistor circuitis not limited to MOSFET of silicon but MOSFET by a compoundsemiconductor of GaAs can be used.

Further, the logical operation circuit having the pass transistorcircuit according to the present invention naturally achieves effects ina reduction in a layout area, a reduction in a wiring amount andreductions in power consumption and a delay time period accompaniedthereby by being applied to a random logic circuit for decoding aninstruction of an RISC type and controlling an instruction executingunit in LSI of a general use processor, a signal processing processor,an image processing processor or the like.

INDUSTRIAL APPLICABILITY

According to the present invention, there can be provided asemiconductor integrated circuit having a pass transistor logicaloperation circuit cell having a small area and capable of reducing powerconsumption and delay.

What is claimed is:
 1. A semiconductor integrated circuit characterizedin that in a semiconductor integrated circuit having a cell comprising alogical operation circuit including at least one pass transistor circuitand at least one output signal amplifier: wherein the pass transistorcircuit in the logical operation circuit includes a first input node, asecond input node and a third input node, a pass transistor output node,a first field effect transistor of a first type or a second type, asource/drain path of which is connected between the first input node andthe pass transistor output node and a second field effect transistor ofthe first type or the second type, a source/drain path of which isconnected between the second input node and the output node; wherein theoutput signal amplifier in the logical operation circuit includes acircuit comprising an input node, an output node, a field effecttransistor of the first type, a drain/source path of which is connectedbetween the output node and first potential and a gate of which respondsto the input node of the output signal amplifier and a field effecttransistor of the second type, a drain/source path of which is connectedbetween the output node of the output signal amplifier and secondpotential and a gate of which responds to the input node; wherein theoutput node of the pass transistor circuit is connected to the input ofthe output signal amplifier; wherein the third input node of the passtransistor circuit is applied with an input signal from outside of thecell; wherein at least two of all of the first input node and the secondinput node of the pass transistor circuit are applied with input signalsfrom outside of the cell; wherein the output node of the output signalamplifier operates to output an output signal to outside of the cell;and wherein when a coordinate system is determined in a direction ofrunning a supply line of the first potential and a supply line of thesecond potential and a direction orthogonal thereto, respectiveterminals by a conductor layer for drawing the input signals fromoutside of the cell and the output signal to outside of the cell arearranged to include terminal grid points disposed at constant intervalsin the coordinate system and grid coordinates of at least one of therespective terminals differ from grid coordinates arranged with at leasttwo or more of the terminals other than the at least one terminal.
 2. Asemiconductor integrated circuit characterized in that in asemiconductor integrated circuit having a cell comprising a logicaloperation circuit including at least one pass transistor circuit and atleast one output signal amplifier: wherein the pass transistor circuitin the logical operation circuit includes a first input node, a secondinput node and a third input node, an output node, a first field effecttransistor of a first type or a second type, a source/drain path ofwhich is connected between the first input node and the output node anda second field effect transistor of the first type or the second type, asource/drain path of which is connected between the second input nodeand the output node; wherein the output signal amplifier in the logicaloperation circuit includes a circuit comprising an input node, an outputnode, a field effect transistor of the first type, a drain/source pathof which is connected between the output node and first potential and agate of which responds to the input node and a field effect transistorof the second type, a drain/source path of which is connected betweenthe output node and second potential and a gate of which responds to theinput node; wherein the output node of the pass transistor circuit isconnected to the input of the output signal amplifier; wherein the thirdinput node of the pass transistor circuit is applied with an inputsignal from outside of the cell; wherein at least two of all of thefirst input node and the second input node of the pass transistorcircuit are applied with input signals from outside of the cell; whereinthe output node of the output signal amplifier operates to output anoutput signal to outside of the cell; and wherein when a coordinatesystem is determined in a direction of running a supply line of thefirst potential and a supply line of the second potential and adirection orthogonal thereto, a terminal from outside of the cell forinputting an input signal applied to the third input node of the passtransistor circuit is arranged to shift to a larger side or a smallerside of the coordinate system rather than terminals from outside of thecell for inputting input signals applied to the first input node and thesecond input node of the pass transistor circuit.
 3. A semiconductorintegrated circuit characterized in that in a semiconductor integratedcircuit having a cell comprising a logical operation circuit includingat least one pass transistor circuit and at least one output signalamplifier: wherein the pass transistor circuit in the logical operationcircuit includes a first input node, a second input node and a thirdinput node, an output node, a first field effect transistor of a firsttype or a second type, a source/drain path of which is connected betweenthe first input node and the output node and a second field effecttransistor of the first type or the second type, a source/drain path ofwhich is connected between the second input node and the output node;wherein the output signal amplifier in the logical operation circuitincludes a circuit comprising an input node, an output node, a fieldeffect transistor of the first type, a drain/source path of which isconnected between the output node and first potential and a gate ofwhich responds to the input node and a field effect transistor of thesecond type, a drain/source path of which is connected between theoutput node and second potential and a gate of which responds to theinput node; wherein the output node of the pass transistor circuit isconnected to the input of the output signal amplifier; and wherein whena coordinate system is determined in a direction of running a supplyline of the first potential and a supply line of the second potential,the two types of the field effect transistors constituting the outputsignal amplifier are arranged to at least one of a cell boundary on aside having smallest coordinate values or a cell boundary on a sidehaving largest coordinate values.
 4. A semiconductor integrated circuitcharacterized in that in a semiconductor integrated circuit having acell comprising a logical operation circuit including at least one passtransistor circuit and at least one output signal amplifier: wherein thepass transistor circuit in the logical operation circuit includes afirst input node, a second input node and a third input node, an outputnode, a first field effect transistor of a first type or a second type,a source/drain path of which is connected between the first input nodeand the output node and a second field effect transistor of the firsttype or the second type, a source/drain path of which is connectedbetween the second input node and the output node; wherein the outputsignal amplifier in the logical operation circuit includes a circuitcomprising an input node, an output node, a field effect transistor ofthe first type, a drain/source path of which is connected between theoutput node and first potential and a gate of which responds to theinput node and a field effect transistor of the second type, adrain/source path of which is connected between the output node andsecond potential and a gate of which responds to the input node; whereinthe output node of the pass transistor circuit is connected to the inputof the output signal amplifier; wherein the third input node of the passtransistor circuit is applied with an input signal from outside of thecell; wherein at least two of all of the first input node and the secondinput node of the pass transistor circuit are applied with input signalsfrom outside of the cell; wherein the output node of the output signalamplifier operates to output an output signal to outside of the cell;and wherein a plurality of the pass transistor circuits are provided inthe cell and the pass transistor circuits are developed to arrange in adirection of running a supply line of the first potential and a supplyline of the second potential.
 5. A semiconductor integrated circuitcharacterized in that in a semiconductor integrated circuit having acell comprising a logical operation circuit including at least one passtransistor circuit and at least one output signal amplifier: wherein thepass transistor circuit in the logical operation circuit includes afirst input node, a second input node and a third input node, an outputnode, a first field effect transistor of a first type or a second type,a source/drain path of which is connected between the first input nodeand the output node and a second field effect transistor of the firsttype or the second type, a source/drain path of which is connectedbetween the second input node and the output node; wherein the outputsignal amplifier in the logical operation circuit includes a circuitcomprising an input node, an output node, a field effect transistor ofthe first type, a drain/source path of which is connected between theoutput node and first potential and a gate of which responds to theinput node and a field effect transistor of the second type, adrain/source path of which is connected between the output node andsecond potential and a gate of which responds to the input node; whereinthe output node of the pass transistor circuit is connected to the inputof the output signal amplifier; wherein the third input node of the passtransistor circuit is applied with an input signal from outside of thecell; wherein at least two of all of the first input node and the secondinput node of the pass transistor circuit are applied with input signalsfrom outside of the cell; wherein the output node of the output signalamplifier operates to output an output signal to outside of the cell;and wherein a plurality of the pass transistor circuits are present atinside of the cell and a width of a source/drain region of the fieldeffect transistor constituting the pass transistor circuit in adirection of running a supply line of the first potential and a supplyline of the second potential is changed depending on locations in thesame source/drain region.
 6. A semiconductor integrated circuitcharacterized in that in a semiconductor integrated circuit having acell comprising a pass transistor logical operation circuit including atleast one pass transistor circuit and at least one output signalamplifier: wherein the pass transistor circuit in the pass transistorlogical operation circuit includes a first input node, a second inputnode and a third input node, an output node, a first field effecttransistor of a first type or a second type, a source/drain path ofwhich is connected between the first input node and the output node anda second field effect transistor of the first type or the second type, asource/drain path of which is connected between the second input nodeand the output node; wherein the output signal amplifier in the logicaloperation circuit includes a circuit comprising an input node, an outputnode, a field effect transistor of the first type, a drain/source pathof which is connected between the output node and first potential and agate of which responds to the input node and a field effect transistorof the second type, a drain/source path of which is connected betweenthe output node and second potential and a gate of which responds to theinput node; wherein the output node of the pass transistor circuit isconnected to the input of the output signal amplifier; and whereinassuming that the cell is arranged contiguous to a CMOS logicaloperation circuit cell constituting a logic by connecting a field effecttransistor of the first type and a field effect transistor of the secondtype in a complementary relationship, a boundary between a semiconductorregion of the second type surrounding the field effect transistor of thefirst type constituting the CMOS logical operation circuit and asemiconductor region of the first type surrounding the field effecttransistor of the second type and a boundary between a semiconductorregion of the second type surrounding the field effect transistor of thefirst type constituting the pass transistor logical operation circuitand a semiconductor region of the first type surrounding the fieldeffect transistor of the second type, are realized to connect linearlyat a portion connecting thereof.
 7. A semiconductor integrated circuitcharacterized in that in a semiconductor integrated circuit having acell comprising a pass transistor logical operation circuit including atleast one pass transistor circuit and at least one output signalamplifier: wherein the pass transistor circuit in the pass transistorlogical operation circuit includes a first input node, a second inputnode and a third input node, an output node, a first field effecttransistor of a first type or a second type, a source/drain path ofwhich is connected between the first input node and the output node anda second field effect transistor of the first type or the second type, asource/drain path of which is connected between the second input nodeand the output node; wherein the output signal amplifier in the logicaloperation circuit includes a circuit comprising an input node, an outputnode, a field effect transistor of the first type, a drain/source pathof which is connected between the output node and first potential and agate of which responds to the input node and a field effect transistorof the second type, a drain/source path of which is connected betweenthe output node and second potential and a gate of which responds to theinput node; wherein the output node of the pass transistor circuit isconnected to the input of the output signal amplifier; and whereinassuming that the cell is arranged contiguous to a CMOS logicaloperation circuit cell constituting a logic by connecting a field effecttransistor of the first type and a field effect transistor of the secondtype in a complementary relationship, a boundary between a semiconductorregion of the second type surrounding the field effect transistor of thefirst type constituting the pass transistor logical operation circuitand a semiconductor region of the first type surrounding the fieldeffect transistor of the second type, is brought to a side of the firstsemiconductor or a side of the second semiconductor and arranged to benonlinear at inside of the cell.
 8. A semiconductor integrated circuitcharacterized in that in a semiconductor integrated circuit including acell comprising a pass transistor logical operation circuit having apair of at least one set of pass transistor circuits and signal polarityinverting circuits and at least one output signal amplifier: wherein thepass transistor circuit in the logical operation circuit includes afirst input node, a second input node and a third input node, an outputnode, a field effect transistor of a first type or a second type, asource/drain path of which is connected between the first input node andthe output node and a field effect transistor of the first type or thesecond type, a source/drain path of which is connected between thesecond input node and the output node; wherein the signal polarityinverting circuit in the logical operation circuit includes a circuitcomprising an input node, an output node, a field effect transistor ofthe first type, a drain/source path of which is connected between theoutput node and first potential and a gate of which responds to theinput node and a field effect transistor of a second type, adrain/source path of which is connected between the output node andsecond potential and a gate of which responds to the input node; whereinthe output signal amplifier in the logical operation circuit includes acircuit comprising an input node, an output node, a field effecttransistor of the first type, a drain/source path of which is connectedbetween the output node and the first potential and a gate of whichresponds to the input node and a field effect transistor of the secondtype, a drain/source path of which is connected between the output nodeand the second potential and a gate of which responds to the input node;wherein the output node of the pass transistor circuit is connected tothe input of the output signal amplifier; wherein the field effecttransistor of the first type constituting the output signal amplifier isprovided with a gate width larger than a gate width of the field effecttransistor of the first type constituting the signal polarity invertingcircuit; and wherein the field effect transistor of the second typeconstituting the output signal amplifier is provided with a gate widthlarger than a gate width of the field effect transistor of the secondtype constituting the signal polarity inverting circuit.
 9. Asemiconductor integrated circuit characterized in that in asemiconductor integrated circuit including a cell comprising a passtransistor logical operation circuit having a pair of at least one setof pass transistor circuits and signal polarity inverting circuits andat least one output signal amplifier: wherein the pass transistorcircuit in the logical operation circuit includes a first input node, asecond input node and a third input node, an output node, a field effecttransistor of a first type or a second type, a source/drain path ofwhich is connected between the first input node and the output node anda field effect transistor of the first type or the second type, asource/drain path of which is connected between the second input nodeand the output node; wherein the signal polarity inverting circuit inthe logical operation circuit includes a circuit comprising an inputnode, an output node, a field effect transistor of the first type, adrain/source path of which is connected between the output node andfirst potential and a gate of which responds to the input node and afield effect transistor of a second type, a drain/source path of whichis connected between the output node and second potential and a gate ofwhich responds to the input node; wherein the output signal amplifier inthe logical operation circuit includes a circuit comprising an inputnode, an output node, a field effect transistor of the first type, adrain/source path of which is connected between the output node and thefirst potential and a gate of which responds to the input node and afield effect transistor of the second type, a drain/source path of whichis connected between the output node and the second potential and a gateof which responds to the input node; wherein the output node of the passtransistor circuit is connected to the input of the output signalamplifier; wherein the field effect transistor constituting the passtransistor circuit is arranged between the first type and the secondtype of the field effect transistors constituting the signal polarityinverting circuit in respect of a direction orthogonal to a direction ofrunning a supply line of the first potential and a supply line of thesecond potential.
 10. A semiconductor integrated circuit characterizedin that in a semiconductor integrated circuit having a cell comprising alogical operation circuit including at least one pass transistor circuitand at least one output signal amplifier: wherein the pass transistorcircuit in the logical operation circuit includes a first input node, asecond input node and a third input node, an output node, a first fieldeffect transistor of a first type or a second type, a source/drain pathof which is connected between the first input node and the output nodeand a second field effect transistor of the first type or the secondtype, a source/drain path of which is connected between the second inputnode and the output node; wherein the output signal amplifier in thelogical operation circuit includes a circuit comprising an input node,an output node, a first field effect transistor of a first type, adrain/source path of which is connected between the output node andfirst potential and a gate of which responds to the input node, a secondfield effect transistor of a second type, a drain/source path of whichis connected between the output node and second potential and a gate ofwhich responds to the input node and a third field effect transistor ofthe first type, a drain/source path of which is connected between theinput node and the first potential and a gate of which responds to theoutput node; and wherein in the output signal amplifier, wire connectionfrom a drain of the third field effect transistor to the gates of thefirst field effect transistor and the second field effect transistor isrealized by passing the wire connection below a supply line of the firstpotential by using a material for a gate terminal of the transistor. 11.A semiconductor integrated circuit characterized in a semiconductorintegrated circuit including a plurality of cells, at least one of saidplurality of cells comprising: a plurality of pass transistor circuitseach including a first input node, a second input node and a third inputnode, an output node, a field effect transistor, a source/drain path isconnected between the first input node and the output node and a fieldeffect transistor, a source/drain path of which is connected between thesecond input node and the output node; and an output signal amplifierincluding a circuit comprising an input node, an output node, a fieldeffect transistor of a first type, a drain/source path of which isconnected between the output node and first potential and a gate ofwhich responds to the input node and a field effect transistor of asecond type, a drain/source path is connected between the output nodeand second potential and a gate of which responds to the input node;wherein the output node of the pass transistor circuit is connected tothe input node of the output signal amplifier; wherein any of the inputnodes of the pass transistor circuit is supplied with an input signalfrom outside of the cell via an inverter arranged at inside of the cell;and wherein the output node of the output signal amplifier operates tooutput an output signal to outside of the cell.
 12. The semiconductorintegrated circuit apparatus according to claim 11, characterized inthat a second cell of the cells includes the well of the first type andthe well of the second type and a boundary line between the well of thefirst type and the well of the second type is in parallel with the firstside of the cell.
 13. The semiconductor integrated circuit apparatusaccording to claim 12, wherein the first cell and the second cell arecontiguous to each other and at a contiguous portion, the boundary linebetween the well of the first type and the well of the second type ofthe first cell coincide with a boundary line between the well of thefirst type and the well of the second type of the second cell.
 14. Thesemiconductor integrated circuit apparatus according to claim 12,wherein in the second cell, input and output terminals are arranged toalign on a straight line.
 15. The semiconductor integrated circuitapparatus according to claim 14, wherein the second cell includes alogical gate constituted by a CMOS transistor.
 16. A semiconductorintegrated circuit apparatus including a plurality of cells havingshapes surrounded by a plurality of sides, wherein a first cell of thecells includes a well of a first type and a well of a second type and aboundary line between the well of the first type and the well of thesecond type is provided with a first portion in parallel with a firstone of the sides and a second portion not in parallel therewith.
 17. Thesemiconductor integrated circuit apparatus according to claim 16,wherein the first portion of the boundary between the wells intersectswith a second and a third side intersecting with the first side.
 18. Thesemiconductor integrated circuit apparatus according to claim 16,wherein the first cell includes an inverter receiving an input signal, apass transistor receiving an output from the inverter and an amplifyingcircuit receiving an output from the pass transistor.
 19. The integratedcircuit apparatus according to claim 16, wherein the first cell includesan inverter of a first CMOS constitution, a transistor constituted bynMOS or pMOS inputting an output from the inverter and an inverterhaving a second CMOS constitution inputting an output from thetransistor.
 20. The integrated circuit apparatus according to claim 16,wherein the first cell includes a first circuit receiving an input fromoutside of the cell, a transistor constituted by nMOS or pMOS inputtingan output from the first circuit and a second circuit inputting anoutput from the transistor wherein an output from the second circuitconstitutes an output to outside of the cell and a gain of the secondcircuit is larger than a gain of the first circuit.
 21. The integratedcircuit apparatus according to claim 16, wherein the first cell includesan inverter receiving an input, a transistor constituted by either oneof nMOS or pMOS inputting the input and an output from the inverter andan amplifying circuit for inputting an output from the transistorwherein an output from the amplifying circuit constitutes an output tooutside of the cell.
 22. The semiconductor integrated circuit apparatusaccording to claim 16, wherein in the first cell, input and outputterminals are arranged not to align on a straight line.
 23. Asemiconductor integrated circuit apparatus, including: a plurality ofcells having a rectangular shape, at least one of the cells including aninput terminal, an inverter of a CMOS constitution inputting an outputfrom the input terminal as a gate input, a transistor constituted bynMOS or pMOS inputting an output from the inverter as a gate input, anamplifying circuit of a CMOS constitution inputting an output from thetransistor as a gate input, and an output terminal outputting an outputfrom the amplifying circuit to outside of the cell; wherein a firstpotential supply line is provided along a first side of the cell, asecond potential supply line is provided along a second side opposed tothe first side, a pMOS transistor and an nMOS transistor constitutingthe amplifying circuit are arranged on cell inner sides of the first andthe second potential supply lines and the transistor is arranged betweenthe pMOS transistor and the nMOS transistor constituting the amplifyingcircuit.
 24. The integrated circuit apparatus according to claim 23,wherein a pMOS transistor and an nMOS transistor constituting theinverter are arranged on the cell inner sides of the first and thesecond potential supply lines, and the transistor is arranged betweenthe pMOS transistor and the nMOS transistor constituting the inverter.25. The integrated circuit apparatus according to claim 23, wherein gateelectrode wirings of the pMOS transistor and the nMOS transistor of theamplifying circuit having the CMOS constitution are arranged along athird side orthogonal to the first side and the second side.
 26. Theintegrated circuit apparatus according to claim 25, when there are aplurality of the transistors constituted by nMOS or pMOS, thetransistors are arranged from a side of a fourth side opposed to thethird side to the third side and when an output from a first transistoramong the plurality of transistors constitutes an input of a secondtransistor, the first transistor is disposed proximate to the fourthside and the second transistor is disposed proximate to the third side.27. The integrated circuit apparatus according to claim 23, wherein asource potential of the transistor constituting the amplifying circuitand a source potential of the transistor constituting the inverter aremade common.